Prozone Engineers

Features Core– Max fCPU: up to 24 MHz, 0 wait states @fCPU 16 MHz– Advanced STM8 core with Harvardarchitecture and 3-stage pipeline– Extended instruction set– Max 20 MIPS @ 24 MHz Memories– Program: up to 128 Kbytes Flash; dataretention 20 years at 55 °C after 10 kcycles– Data: up to 2 Kbytes true data EEPROM;endurance 300 kcycles– RAM: up to 6 Kbytes Clock, reset and supply management– 2.95 to 5.5 V operating voltage– Low power crystal resonator oscillator– External clock input– Internal, user-trimmable 16 MHz RC– Internal low power 128 kHz RC– Clock security system with clock monitor– Wait, active-halt, & halt low power modes– Peripheral clocks switched off individually– Permanently active, low consumptionpower-on and power-down reset Interrupt management– Nested interrupt controller with 32interrupts– Up to 37 external interrupts on 6 vectors Timers– 2x 16-bit general purpose timers, with 2+3CAPCOM channels (IC, OC or PWM)– Advanced control timer: 16-bit, 4 CAPCOMchannels, 3 complementary outputs, deadtime insertion and flexible synchronization– 8-bit basic timer with 8-bit prescaler– Auto wakeup timer– Window watchdog, independent watchdog Communications interfaces– High speed 1 Mbit/s active beCAN 2.0B– UART with clock output for synchronousoperation - LIN master mode– UART with LIN 2.1 compliant, master/slavemodes and automatic resynchronization– SPI interface up to 10 Mbit/s– I2C interface up to 400 Kbit/s 10-bit ADC with up to 16 channels I/Os– Up to 68 I/Os on an 80-pin packageincluding 18 high sink outputs– Highly robust I/O design, immune againstcurrent injection– Development support– Single wire interface module (SWIM) anddebug module (DM) 96-bit unique ID key for each device

Additional Information:

• Delivery Time: Lead time 7-10 working days

Features Core– Max fCPU: up to 24 MHz, 0 wait states @fCPU 16 MHz– Advanced STM8 core with Harvardarchitecture and 3-stage pipeline– Extended instruction set– Max 20 MIPS @ 24 MHz Memories– Program: up to 128 Kbytes Flash; dataretention 20 years at 55 °C after 10 kcycles– Data: up to 2 Kbytes true data EEPROM;endurance 300 kcycles– RAM: up to 6 Kbytes Clock, reset and supply management– 2.95 to 5.5 V operating voltage– Low power crystal resonator oscillator– External clock input– Internal, user-trimmable 16 MHz RC– Internal low power 128 kHz RC– Clock security system with clock monitor– Wait, active-halt, & halt low power modes– Peripheral clocks switched off individually– Permanently active, low consumptionpower-on and power-down reset Interrupt management– Nested interrupt controller with 32interrupts– Up to 37 external interrupts on 6 vectors Timers– 2x 16-bit general purpose timers, with 2+3CAPCOM channels (IC, OC or PWM)– Advanced control timer: 16-bit, 4 CAPCOMchannels, 3 complementary outputs, deadtime insertion and flexible synchronization– 8-bit basic timer with 8-bit prescaler– Auto wakeup timer– Window watchdog, independent watchdog Communications interfaces– High speed 1 Mbit/s active beCAN 2.0B– UART with clock output for synchronousoperation - LIN master mode– UART with LIN 2.1 compliant, master/slavemodes and automatic resynchronization– SPI interface up to 10 Mbit/s– I2C interface up to 400 Kbit/s 10-bit ADC with up to 16 channels I/Os– Up to 68 I/Os on an 80-pin packageincluding 18 high sink outputs– Highly robust I/O design, immune againstcurrent injection– Development support– Single wire interface module (SWIM) anddebug module (DM) 96-bit unique ID key for each device

Additional Information:

• Item Code: 25000
• Delivery Time: 1-2 weeks

Features Core– Max fCPU: up to 24 MHz, 0 wait states @fCPU 16 MHz– Advanced STM8 core with Harvardarchitecture and 3-stage pipeline– Extended instruction set– Max 20 MIPS @ 24 MHz Memories– Program: up to 128 Kbytes Flash; dataretention 20 years at 55 °C after 10 kcycles– Data: up to 2 Kbytes true data EEPROM;endurance 300 kcycles– RAM: up to 6 Kbytes Clock, reset and supply management– 2.95 to 5.5 V operating voltage– Low power crystal resonator oscillator– External clock input– Internal, user-trimmable 16 MHz RC– Internal low power 128 kHz RC– Clock security system with clock monitor– Wait, active-halt, & halt low power modes– Peripheral clocks switched off individually– Permanently active, low consumptionpower-on and power-down reset Interrupt management– Nested interrupt controller with 32interrupts– Up to 37 external interrupts on 6 vectors Timers– 2x 16-bit general purpose timers, with 2+3CAPCOM channels (IC, OC or PWM)– Advanced control timer: 16-bit, 4 CAPCOMchannels, 3 complementary outputs, deadtime insertion and flexible synchronization– 8-bit basic timer with 8-bit prescaler– Auto wakeup timer– Window watchdog, independent watchdog Communications interfaces– High speed 1 Mbit/s active beCAN 2.0B– UART with clock output for synchronousoperation - LIN master mode– UART with LIN 2.1 compliant, master/slavemodes and automatic resynchronization– SPI interface up to 10 Mbit/s– I2C interface up to 400 Kbit/s 10-bit ADC with up to 16 channels I/Os– Up to 68 I/Os on an 80-pin packageincluding 18 high sink outputs– Highly robust I/O design, immune againstcurrent injection– Development support– Single wire interface module (SWIM) anddebug module (DM) 96-bit unique ID key for each device

Additional Information:

• Production Capacity: 25000
• Delivery Time: 10-14 working days

Features Core– Max fCPU: up to 24 MHz, 0 wait states @fCPU 16 MHz– Advanced STM8 core with Harvardarchitecture and 3-stage pipeline– Extended instruction set– Max 20 MIPS @ 24 MHz Memories– Program: up to 128 Kbytes Flash; dataretention 20 years at 55 °C after 10 kcycles– Data: up to 2 Kbytes true data EEPROM;endurance 300 kcycles– RAM: up to 6 Kbytes Clock, reset and supply management– 2.95 to 5.5 V operating voltage– Low power crystal resonator oscillator– External clock input– Internal, user-trimmable 16 MHz RC– Internal low power 128 kHz RC– Clock security system with clock monitor– Wait, active-halt, & halt low power modes– Peripheral clocks switched off individually– Permanently active, low consumptionpower-on and power-down reset Interrupt management– Nested interrupt controller with 32interrupts– Up to 37 external interrupts on 6 vectors Timers– 2x 16-bit general purpose timers, with 2+3CAPCOM channels (IC, OC or PWM)– Advanced control timer: 16-bit, 4 CAPCOMchannels, 3 complementary outputs, deadtime insertion and flexible synchronization– 8-bit basic timer with 8-bit prescaler– Auto wakeup timer– Window watchdog, independent watchdog Communications interfaces– High speed 1 Mbit/s active beCAN 2.0B– UART with clock output for synchronousoperation - LIN master mode– UART with LIN 2.1 compliant, master/slavemodes and automatic resynchronization– SPI interface up to 10 Mbit/s– I2C interface up to 400 Kbit/s 10-bit ADC with up to 16 channels I/Os– Up to 68 I/Os on an 80-pin packageincluding 18 high sink outputs– Highly robust I/O design, immune againstcurrent injection– Development support– Single wire interface module (SWIM) anddebug module (DM) 96-bit unique ID key for each device

Additional Information:

• Delivery Time: Lead Time 1-2 Weeks

Features Core– Max fCPU: up to 24 MHz, 0 wait states @fCPU 16 MHz– Advanced STM8 core with Harvardarchitecture and 3-stage pipeline– Extended instruction set– Max 20 MIPS @ 24 MHz Memories– Program: up to 128 Kbytes Flash; dataretention 20 years at 55 °C after 10 kcycles– Data: up to 2 Kbytes true data EEPROM;endurance 300 kcycles– RAM: up to 6 Kbytes Clock, reset and supply management– 2.95 to 5.5 V operating voltage– Low power crystal resonator oscillator– External clock input– Internal, user-trimmable 16 MHz RC– Internal low power 128 kHz RC– Clock security system with clock monitor– Wait, active-halt, & halt low power modes– Peripheral clocks switched off individually– Permanently active, low consumptionpower-on and power-down reset Interrupt management– Nested interrupt controller with 32interrupts– Up to 37 external interrupts on 6 vectors Timers– 2x 16-bit general purpose timers, with 2+3CAPCOM channels (IC, OC or PWM)– Advanced control timer: 16-bit, 4 CAPCOMchannels, 3 complementary outputs, deadtime insertion and flexible synchronization– 8-bit basic timer with 8-bit prescaler– Auto wakeup timer– Window watchdog, independent watchdog Communications interfaces– High speed 1 Mbit/s active beCAN 2.0B– UART with clock output for synchronousoperation - LIN master mode– UART with LIN 2.1 compliant, master/slavemodes and automatic resynchronization– SPI interface up to 10 Mbit/s– I2C interface up to 400 Kbit/s 10-bit ADC with up to 16 channels I/Os– Up to 68 I/Os on an 80-pin packageincluding 18 high sink outputs– Highly robust I/O design, immune againstcurrent injection– Development support– Single wire interface module (SWIM) anddebug module (DM) 96-bit unique ID key for each device

Additional Information:

• Delivery Time: Lead Time 7-10 Working days

Features Core– Max fCPU: up to 24 MHz, 0 wait states @fCPU 16 MHz– Advanced STM8 core with Harvardarchitecture and 3-stage pipeline– Extended instruction set– Max 20 MIPS @ 24 MHz Memories– Program: up to 128 Kbytes Flash; dataretention 20 years at 55 °C after 10 kcycles– Data: up to 2 Kbytes true data EEPROM;endurance 300 kcycles– RAM: up to 6 Kbytes Clock, reset and supply management– 2.95 to 5.5 V operating voltage– Low power crystal resonator oscillator– External clock input– Internal, user-trimmable 16 MHz RC– Internal low power 128 kHz RC– Clock security system with clock monitor– Wait, active-halt, & halt low power modes– Peripheral clocks switched off individually– Permanently active, low consumptionpower-on and power-down reset Interrupt management– Nested interrupt controller with 32interrupts– Up to 37 external interrupts on 6 vectors Timers– 2x 16-bit general purpose timers, with 2+3CAPCOM channels (IC, OC or PWM)– Advanced control timer: 16-bit, 4 CAPCOMchannels, 3 complementary outputs, deadtime insertion and flexible synchronization– 8-bit basic timer with 8-bit prescaler– Auto wakeup timer– Window watchdog, independent watchdog Communications interfaces– High speed 1 Mbit/s active beCAN 2.0B– UART with clock output for synchronousoperation - LIN master mode– UART with LIN 2.1 compliant, master/slavemodes and automatic resynchronization– SPI interface up to 10 Mbit/s– I2C interface up to 400 Kbit/s 10-bit ADC with up to 16 channels I/Os– Up to 68 I/Os on an 80-pin packageincluding 18 high sink outputs– Highly robust I/O design, immune againstcurrent injection– Development support– Single wire interface module (SWIM) anddebug module (DM) 96-bit unique ID key for each device

Additional Information:

• Delivery Time: 10-14 working days

Features Core– Max fCPU: up to 24 MHz, 0 wait states @fCPU 16 MHz– Advanced STM8 core with Harvardarchitecture and 3-stage pipeline– Extended instruction set– Max 20 MIPS @ 24 MHz Memories– Program: up to 128 Kbytes Flash; dataretention 20 years at 55 °C after 10 kcycles– Data: up to 2 Kbytes true data EEPROM;endurance 300 kcycles– RAM: up to 6 Kbytes Clock, reset and supply management– 2.95 to 5.5 V operating voltage– Low power crystal resonator oscillator– External clock input– Internal, user-trimmable 16 MHz RC– Internal low power 128 kHz RC– Clock security system with clock monitor– Wait, active-halt, & halt low power modes– Peripheral clocks switched off individually– Permanently active, low consumptionpower-on and power-down reset Interrupt management– Nested interrupt controller with 32interrupts– Up to 37 external interrupts on 6 vectors Timers– 2x 16-bit general purpose timers, with 2+3CAPCOM channels (IC, OC or PWM)– Advanced control timer: 16-bit, 4 CAPCOMchannels, 3 complementary outputs, deadtime insertion and flexible synchronization– 8-bit basic timer with 8-bit prescaler– Auto wakeup timer– Window watchdog, independent watchdog Communications interfaces– High speed 1 Mbit/s active beCAN 2.0B– UART with clock output for synchronousoperation - LIN master mode– UART with LIN 2.1 compliant, master/slavemodes and automatic resynchronization– SPI interface up to 10 Mbit/s– I2C interface up to 400 Kbit/s 10-bit ADC with up to 16 channels I/Os– Up to 68 I/Os on an 80-pin packageincluding 18 high sink outputs– Highly robust I/O design, immune againstcurrent injection– Development support– Single wire interface module (SWIM) anddebug module (DM) 96-bit unique ID key for each device

Additional Information:

• Delivery Time: 7-10 working days

Features Core– Max fCPU: up to 24 MHz, 0 wait states @fCPU 16 MHz– Advanced STM8 core with Harvardarchitecture and 3-stage pipeline– Extended instruction set– Max 20 MIPS @ 24 MHz Memories– Program: up to 128 Kbytes Flash; dataretention 20 years at 55 °C after 10 kcycles– Data: up to 2 Kbytes true data EEPROM;endurance 300 kcycles– RAM: up to 6 Kbytes Clock, reset and supply management– 2.95 to 5.5 V operating voltage– Low power crystal resonator oscillator– External clock input– Internal, user-trimmable 16 MHz RC– Internal low power 128 kHz RC– Clock security system with clock monitor– Wait, active-halt, & halt low power modes– Peripheral clocks switched off individually– Permanently active, low consumptionpower-on and power-down reset Interrupt management– Nested interrupt controller with 32interrupts– Up to 37 external interrupts on 6 vectors Timers– 2x 16-bit general purpose timers, with 2+3CAPCOM channels (IC, OC or PWM)– Advanced control timer: 16-bit, 4 CAPCOMchannels, 3 complementary outputs, deadtime insertion and flexible synchronization– 8-bit basic timer with 8-bit prescaler– Auto wakeup timer– Window watchdog, independent watchdog Communications interfaces– High speed 1 Mbit/s active beCAN 2.0B– UART with clock output for synchronousoperation - LIN master mode– UART with LIN 2.1 compliant, master/slavemodes and automatic resynchronization– SPI interface up to 10 Mbit/s– I2C interface up to 400 Kbit/s 10-bit ADC with up to 16 channels I/Os– Up to 68 I/Os on an 80-pin packageincluding 18 high sink outputs– Highly robust I/O design, immune againstcurrent injection– Development support– Single wire interface module (SWIM) anddebug module (DM) 96-bit unique ID key for each device

Additional Information:

• Delivery Time: 1-2 Weeks

Features Core– Max fCPU: up to 24 MHz, 0 wait states @fCPU 16 MHz– Advanced STM8 core with Harvardarchitecture and 3-stage pipeline– Extended instruction set– Max 20 MIPS @ 24 MHz Memories– Program: up to 128 Kbytes Flash; dataretention 20 years at 55 °C after 10 kcycles– Data: up to 2 Kbytes true data EEPROM;endurance 300 kcycles– RAM: up to 6 Kbytes Clock, reset and supply management– 2.95 to 5.5 V operating voltage– Low power crystal resonator oscillator– External clock input– Internal, user-trimmable 16 MHz RC– Internal low power 128 kHz RC– Clock security system with clock monitor– Wait, active-halt, & halt low power modes– Peripheral clocks switched off individually– Permanently active, low consumptionpower-on and power-down reset Interrupt management– Nested interrupt controller with 32interrupts– Up to 37 external interrupts on 6 vectors Timers– 2x 16-bit general purpose timers, with 2+3CAPCOM channels (IC, OC or PWM)– Advanced control timer: 16-bit, 4 CAPCOMchannels, 3 complementary outputs, deadtime insertion and flexible synchronization– 8-bit basic timer with 8-bit prescaler– Auto wakeup timer– Window watchdog, independent watchdog Communications interfaces– High speed 1 Mbit/s active beCAN 2.0B– UART with clock output for synchronousoperation - LIN master mode– UART with LIN 2.1 compliant, master/slavemodes and automatic resynchronization– SPI interface up to 10 Mbit/s– I2C interface up to 400 Kbit/s 10-bit ADC with up to 16 channels I/Os– Up to 68 I/Os on an 80-pin packageincluding 18 high sink outputs– Highly robust I/O design, immune againstcurrent injection– Development support– Single wire interface module (SWIM) anddebug module (DM) 96-bit unique ID key for each device

Additional Information:

• Delivery Time: 1-2 Weeks

Features Core– Max fCPU: up to 24 MHz, 0 wait states @fCPU 16 MHz– Advanced STM8 core with Harvardarchitecture and 3-stage pipeline– Extended instruction set– Max 20 MIPS @ 24 MHz Memories– Program: up to 128 Kbytes Flash; dataretention 20 years at 55 °C after 10 kcycles– Data: up to 2 Kbytes true data EEPROM;endurance 300 kcycles– RAM: up to 6 Kbytes Clock, reset and supply management– 2.95 to 5.5 V operating voltage– Low power crystal resonator oscillator– External clock input– Internal, user-trimmable 16 MHz RC– Internal low power 128 kHz RC– Clock security system with clock monitor– Wait, active-halt, & halt low power modes– Peripheral clocks switched off individually– Permanently active, low consumptionpower-on and power-down reset Interrupt management– Nested interrupt controller with 32interrupts– Up to 37 external interrupts on 6 vectors Timers– 2x 16-bit general purpose timers, with 2+3CAPCOM channels (IC, OC or PWM)– Advanced control timer: 16-bit, 4 CAPCOMchannels, 3 complementary outputs, deadtime insertion and flexible synchronization– 8-bit basic timer with 8-bit prescaler– Auto wakeup timer– Window watchdog, independent watchdog Communications interfaces– High speed 1 Mbit/s active beCAN 2.0B– UART with clock output for synchronousoperation - LIN master mode– UART with LIN 2.1 compliant, master/slavemodes and automatic resynchronization– SPI interface up to 10 Mbit/s– I2C interface up to 400 Kbit/s 10-bit ADC with up to 16 channels I/Os– Up to 68 I/Os on an 80-pin packageincluding 18 high sink outputs– Highly robust I/O design, immune againstcurrent injection– Development support– Single wire interface module (SWIM) anddebug module (DM) 96-bit unique ID key for each device

Additional Information:

• Production Capacity: 2500
• Delivery Time: 1-2 WEEKS